Digital Verification Engineer I Jobs in Delhi,Bangalore,Bhubaneswar – Asiczen Technologies
Asiczen Technologies
Digital Verification Engineer I
Eligibility : ME/M.Tech(CSE, EEE, Electrical, ECE, VLSI Design), BE/B.Tech(CSE, EEE, ECE, Electronics & Instrumentation)
Location : Hyderabad, Delhi, Bangalore, Bhubaneswar, Noida
Last Date : 26 Jan 2017
Salary : 175000 – 425000 Rs Per Year
Experience Required: 0-2 Years
Skills: Perl, VLSI, Python, Verilog
Asiczen Technologies – Job DetailsDate of posting:18 Jan 17
Job Responsibilities
Understand specification and develop UVCs.
Debug testcase failures in existing environments.
Responsible for writing required documentation on test benches and/or test plans.
Develop testplans from specifications and create UVM environments.
Scripting in Perl, Python, Shell scripts.
Education/Industry Experience
BE/BTech/MS/MSc/MTech/ME: Electrical, Electronics, VLSI or Computer Science.
Expected experience is about 0-2 years in the relevant area.
Skills:
Associated with Verification especially using industry standard protocols & methodology
Must have strong System Verilog/ UVM concepts
Experience in building UVM environments or UVCs
Good problem-solving skills
Should have good programming knowledge (C, C++)
Scripting knowledge (Perl, Python, Makefile) is an added advantage
Hiring Process : Written-test, Face to Face Interview
Job Role: IT Software-Engineer
